1. Field of the Invention
The present invention relates to a semiconductor memory device having a plurality of memory cell array blocks, each of which has 2K+a (k and a are an integer, respectively) word lines, and a method for generating a block selection signal for selecting said word lines.
2. Description of the Related Art
In general, a semiconductor memory device includes a plurality of memory cell array blocks and each of the memory cell array blocks has 2k (k is an integer) word lines. Data is read out and written into a memory cell array block which is selected in response to a corresponding block selection signal.
FIG. 1 is a block diagram of a semiconductor memory device with a plurality of memory cell array blocks. FIG. 1 illustrates a conventional method of generating a block selection signal for selecting one memory cell array block from a plurality of memory cell array blocks. As shown in FIG. 1, the semiconductor memory device includes 16 memory cell array blocks BLK1-BLK16 and each of the blocks has 512 (2k, k is 9) word lines WL1-WL512.
In FIG. 1, row address signals RA12B, RA11B, RA10B, and RA9B represent inverted signals of address signals RA12, RA11, RA10, and RA9, respectively. Block selection signals for selecting one of the memory cell array blocks BLK1-BLK16 are generated by decoding 4-bit row address signals RA12-RA9. Word line selection signals for selecting a word line out of 512 word lines in a memory cell array block are generated by decoding 9-bit row address signals RA0-RA8.
A conventional method for generating the block selection signals for selecting each of the 16 memory cell array blocks BLK1-BLK16 will be described below.
A block selection signal for selecting the first block BLK1 is generated when the row address signals RA12B, RA11B, RA10B and RA9B are all at a logic xe2x80x9chighxe2x80x9d level. A block selection signal for selecting the second block BLK2 is generated when the row address signals RA12B, RA11B, RA10B and RA9 are all at a logic xe2x80x9chighxe2x80x9d level. A block selection signal for selecting the third block BLK3 is generated when the row address signals RA12B, RA11B, RA10 and RA9B are all at a logic xe2x80x9chighxe2x80x9d level. A block selection signal for selecting the fourth block BLK4 is generated when the row address signals RA12B, RA11B, RA10 and RA9 are all in a logic xe2x80x9chighxe2x80x9d level. Similarly, a block selection signal for selecting the sixteenth block BLK16 is generated when the row address signals RA12, RA11, RA10 and RA9 have a logic xe2x80x9chighxe2x80x9d level.
FIG. 2 is a schematic block diagram showing the memory cell array block from FIG. 1 in more detail. Each of the memory cell array blocks BLK1-BLK16 includes a plurality of pairs of bit lines BL1-BL1B, BL2-BL2B, BL3-BL3B, etc.
Between each of the memory cell array blocks BLK1-BLK16, a pre-charge circuit 14-1 is arranged at the right end of bit line pairs BL1-BL1B, BL2-BL2B and a pre-charge circuit 14-2 is arranged at the left end of bit line pairs BL1-BL1B, BL2-BL2B.
Bit line isolation circuits 12-1 are arranged on the left side of a corresponding pre-charge circuit 14-1 and bit line isolation circuits 12-2 are arranged on the right side of a corresponding pre-charge circuit 14-2. Bit line isolation circuits 12-1 are comprised of two NMOS transistors N1 and N2. Bit line isolation circuits 12-2 are comprised of two NMOS transistors N3 and N4.
Sense amplifiers 10-1, 10-12 are connected to each of the corresponding bit line pairs by being interposed between the corresponding pre-charge circuit 14-1 or 14-2 and the bit line isolation circuit 12-1 or 12-2. The sense amplifier 10-1 is arranged on the left side of the first memory cell array block BLK1 and is coupled to the the bit line isolation circuit 12-1 by the bit line pair belonging to the first memory cell array block BLK1. The sense amplifier 10-12 is arranged on the right side of the sixteenth memory cell array block BLK16 and is coupled to the the bit line isolation circuit 12-2 by the bit line pair belonging to the sixteenth memory cell array block BLK16.
The sense amplifier 10-12 is arranged in a space between adjacent memory cell array blocks BLK1-BLK16 by being interposed between the corresponding bit line isolation circuits 12-1, 12-2. The sense amplifier 10-12 is shared by two memory cell array blocks which are arranged on the left side thereof and on the right side thereof, respectively. Each of the sense amplifiers 10-12 is coupled to each pair of the bit lines BL1-BL1B, BL2-BL2B, . . . , in two memory cell array blocks arranged on either side of the sense amplifier 10-12.
As shown in FIG. 1 and FIG. 2, the semiconductor memory device in accordance with the conventional art has 2k memory cell arrays.
In FIG. 2, signals ISO1-ISO16 are the block selection signals for selecting one of the memory cell array blocks BLK1-BLK16.
Operation of the memory cell array shown in FIG. 2 is as follows:
During pre-charging operation, the pre-charge circuits 14-1, 14-2 pre-charge the pairs of bit lines BL1-BL1B, BL2-BL2B, etc.
After a word line WL1 is selected, charge sharing occurs between the pairs of bit lines BL1-BL1B, BL2-BL2B, etc, that are connected to the memory cells that are in turn coupled to the selected word line WL1 and the capacitors belonging to the corresponding memory cells.
After that, the signal ISO1 is generated with a xe2x80x9chighxe2x80x9d logic level when a block selection signal for selecting the memory cell block BLK1 is generated. As a result, the NMOS transistors N1-N4 of the bit line isolation circuits 12-1, 12-2 are turned on and the sense amplifiers 10-1, 10-12 are operated to amplify data signals from the pairs of bit lines.
As shown in FIG. 1 and FIG. 2, seventeen amplifying circuits for amplifying data signals produced by the pairs of bit lines are needed for the semiconductor memory device having 16 memory cell array blocks BLK1-BLK16. For example, fifteen of the seventeen amplifying circuits are arranged in every corresponding space between adjacent memory cell array blocks BLK1-BLK16 and two amplifying circuits are arranged beside the outermost memory cell array blocks BLK1, BLK16.
That is, a conventional semiconductor memory device requires seventeen data amplifying circuits, to such an extent that the memory cell array parts dominates a large area of the semiconductor substrate. Accordingly, it is difficult to reduce the chip size including the semiconductor memory device therein.
It is an object of the present invention to provide a semiconductor memory device having a reduced lay-out area dominated by the memory cell array.
It is another object of the present invention to provide a method of generating a block selection signal for a semiconductor memory device having 2k+a word lines in each memory cell array block.
In accordance with one aspect of the present invention, there is provided a semiconductor memory device including a memory cell array having 2n (n is an integer) groups of memory cell array blocks, each of the group having m (m is an integer) memory cell array blocks, each of the memory cell array blocks having 2K+a (K and a are integers) word lines, and a block selection signal generating circuit for generating a block selection signal for selecting one of the memory cell array blocks by decoding a plurality of row address signals.
The block selection signal generating circuit comprises a first-step-block-selection signal generating circuit for generating a first-step-block-selection signal for selecting one group out of the 2n groups, a second-step-block-selection signal generating circuit for generating a second-step-block-selection signal for selecting one memory cell array block in the every group, a third-step-block-selection signal generating circuit for generating a third-step-block-selection signal for selecting a memory cell array block out of the (mxc3x972n) memory cell array blocks in response to the first-step-block-selection signal and the second-step-block-selection signal.
In accordance with another aspect of the present invention, a method for generating a block selection signal is provided for a semiconductor memory device having a memory cell array including 2n (n is an integer) groups comprised of m (m is an integer) memory cell array blocks, each of the memory cell array blocks having 2k+a (k, a are integers) word lines, comprising generating a block selection signal for selecting a memory cell array block out of (mxc3x972n) memory cell array blocks by decoding row address.
Generating a block selection signal comprises: generating first block selection signals for selecting each group of 2n groups, generating second block selection signals for selecting in every group, and generating third block selection signals for each memory cell array block each memory cell array block out of the (mxc3x972n) memory cell array blocks by receiving the first block selection signals and the second block selection signals.